Methods for mask repattern process

ABSTRACT

The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 09/754,671,filed Jan. 4, 2001, now U.S. Pat. No. 6,365,501, issused Apr. 2, 2002,which is a continuation of application Ser. No. 09/464,988, filed Dec.16, 1999, now U.S. Pat. No. 6,211,052, issued Apr. 3, 2001, which is acontinuation of application Ser. No. 09/179,310, filed Oct. 27, 1998,now U.S. Pat. No. 6,083,820 issued Jul. 4, 2000, which is a continuationof application Ser. No. 08/767,162, filed Dec. 16, 1996, now U.S. Pat.No. 5,851,911, issued Dec. 22, 1998, which is a continuation-in-part ofapplication Ser. No. 08/612,059, filed Mar. 7, 1996, now U.S. Pat. No.6,072,236, issued Jun. 6, 2000, and application Ser. No. 08/682,141,filed Jul. 17, 1996, now U.S. Pat. No. 5,736,456, issued Apr. 7, 1998.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of repatterning circuits andthe like on semiconductor devices. More specifically, the presentinvention relates to a method for forming conductive bumps on a die forflip-chip type attachment to a printed circuit board, or the like, afterthe repatterning of a circuit on a semiconductor device. In particular,the present invention relates to a method for forming under bumpmetallization pads, which method utilizes simplified or a minimal numberof masking steps.

2. State of the Art

The following terms and acronyms will be used throughout the applicationand are defined as follows:

BGA—Ball Grid Array: An array of minute solder balls disposed onconductive locations of an active surface of a semiconductor die,wherein the solder balls are refluxed for simultaneous attachment andelectrical communication of the semiconductor die to conductors of aprinted circuit board or other substrate.

Flip-Chip: A chip or die that has a pattern or array of terminationsspaced around the active surface of the die for face-down mounting ofthe die to a substrate.

Flip-Chip Attachment: A method of attaching a semiconductor die to asubstrate in which the die is inverted so that the connecting conductorpads on the face of the device are set on mirror-image pads ofconductive traces carried by the substrate and bonded thereto by solderreflux. Also, sometimes known as C4 attachment (“Controlled CollapseChip Connection”).

SLICC—Slightly Larger than Integrated Circuit Carrier: An array ofminute solder balls disposed on an attachment surface of a semiconductordie similar to a BGA, but having a smaller solder ball diameter andpitch than a BGA.

High performance microelectronic devices may comprise a number offlip-chips having a BGA or a SLICC attached to a ceramic or siliconsubstrate or printed circuit board (“PCB”) such as an FR4 board forelectrical interconnection to other microelectronic devices. Forexample, a very large scale integration (“VLSI”) chip may beelectrically connected to a substrate, printed circuit board, or othernext higher level packaging carrier member using solder balls or solderbumps. This connection technology may be referred to generically as“flip-chip” or “C4” attachment.

Flip-chip attachment requires the formation of contact terminals atflip-chip contact sites on the semiconductor die, each site consistingof a metal pad with a lead/tin solder ball formed thereon. Flip-chipattachment also requires the formation of solder joinable sites (“pads”)on the metal conductors of the PCB or other substrate or carrier whichare a mirror-image of the solder ball arrangement on the flip-chip. Thepads on the substrate are usually surrounded by non-solderable barriersso that when the solder balls of the chip contact sites are aligned withthe substrate pads and “reflow”, the surface tension of the liquifiedsolder element supports the semiconductor chip above the substrate.After cooling, the chip is essentially welded face-down by very small,closely spaced, solidified solder interconnections. An underfillencapsulant is generally disposed between the semiconductor die and thesubstrate for environmental protection and to further enhance themechanical attachment of the die to the substrate.

FIGS. 1a-h show a contemporary, prior art method of forming a conductiveball arrangement on a flip-chip. First, a plurality of semiconductordevices, such as dice including integrated circuitry (not shown), isfabricated on a face surface 12 of a semiconductor wafer 10. A pluralityof conductive traces 14 is then formed on the semiconductor wafer facesurface 12 positioned to contact circuitry of the respectivesemiconductor elements (not shown), as in FIG. 1a. A passivation film16, such as at least one layer of SiO₂ film, Si₃N₄ film, or the like, isformed over the semiconductor wafer face surface 12 as well as theconductive traces 14, as shown in FIG. 1b. A first layer ofetchant-resistive photoresist film 18 is subsequently applied to a facesurface 20 of the passivation film 16. The first photoresist film 18 isnext masked, exposed, and stripped to form desired openings (oneillustrated) in the first photoresist film 18. The passivation film 16is then etched through the opening in photoresist film 18 to form a via22 with either sloped edges or walls 26, or even substantially verticalwalls, and which exposes a face surface 24 of the conductive trace 14,as shown in FIG. 1c. First photoresist film 18 is then stripped, asshown in FIG. 1d.

FIG. 1e shows metal layers 28, 30, and 32 applied over the passivationfilm face surface 20 as well as the via 22 to form a multi-layer underbump metallurgy (UBM) 34 by chemical vapor deposition (CVD),plasma-enhanced chemical vapor deposition (PECVD), physical vapordeposition (PVD), either sputtering or evaporation. The metal layersusually comprise chromium for the first or base adhesion layer 28,chromium-copper alloy for a second, intermediate layer 30, and copperfor the third, outer soldering layer 32. Additionally, a fourth metallayer (not shown) of flashed gold is occasionally placed atop the copperthird layer 32 to prevent oxidation of the copper. Nickel, palladium,and platinum have also been employed as the outer or soldering layer 32.Furthermore, titanium or titanium/tungsten alloys have been used asalternatives to chromium for the adhesion layer. Two-layer UBMs with agold flash coating are also known, as are single-layer UBMs.

A second layer of etchant-resistive photoresist film 35 is then masked,exposed, and stripped to form at least one second etchant-resistiveblock 36 over the vias 22, as shown in FIG. 1f. The metal layers 28, 30,and 32 surrounding vias 22 are then etched and the etchant-resistiveblock 36 is stripped to form a discrete UBM pad 40, as shown in FIG. 1g.A solder bump 42 is then formed on the UBM pad 40, as shown in FIG. 1h,by any known industry technique, such as stenciling, screen printing,electroplating, electroless plating, evaporation or the like.

The UBM pads 40 can also be made by selectively depositing the metallayers by evaporation through a mask (or photoengraving) onto thepassivation film face surface 20 as well as the via 22 such that themetal layers 28, 30, and 32 correspond to the exposed portions of theconductive traces 14.

Solder balls are generally formed of lead and tin. High concentrationsof lead are sometimes used to make the bump more compatible withsubsequent processing steps. Tin is added to strengthen bonding (to suchmetal as copper) and serves as an antioxidant. High-temperature (meltingpoint of approximately 315 degrees Centigrade) solder alloy has beenused to join chips to thick ceramic substrates and multi-layer cofferedceramic interface modules. Joining chips to organic carriers, such aspolyamide-glass, polyamide-aramid, and the like, as well as the printedwiring boards, requires lower temperatures which may be obtained byusing 63Sn/37Pb solder (melting point 183 degrees Centigrade) andvarious Pb/In alloys, such as 50Pb/50In (melting point of approximately220 degrees Centigrade). Lower melting point alloys (down to 60 degreesCentigrade) have been used to bump very temperature-sensitive chips,such as GaAs and superconducting Josephson junctions.

Numerous techniques have been devised to improve the UBM and formationof solder bumps for flip-chips. For example, U.S. Pat. No. 4,360,142,issued Nov. 23, 1982, to Carpenter et al., relates to forming multiplelayer UBM pads between a semiconductor device and a supporting substrateparticularly suited to high stress use conditions that generate thermalgradients in the interconnection.

U.S. Pat. No. 5,137,845, issued Aug. 11, 1992, to Lochon et al.,pertains to a method of forming solder bumps and UBM pads of a desiredsize on semiconductor chips based on an involved photolithographictechnique such that the dimensions of the solder bumps can be reduced inorder to increase the number of bumps on a chip.

U.S. Pat. No. 5,470,787, issued on Nov. 28, 1995, to Greer, relates to asubstantially cylindrical layered solder bump wherein the bump comprisesa lower tin layer adjacent to the UBM pad, a thick lead layer, and anupper tin layer to provide an optimized, localized eutectic formation atthe top of the bump during solder reflow.

U.S. Pat. Nos. 4,906,341, 5,293,006, 5,341,946, and 5,480,835 alsodisclose materials and techniques for forming UBM pads and solder bumps.

All of the above patents and prior art techniques for forming UBM padsand solder bumps are relatively complex and require a substantial numberof discrete steps and number of masking steps to form the flip-chipconductive bumps. Therefore, it would be advantageous to develop anefficient technique for forming conductive bump structures on aflip-chip to eliminate as many steps as required by present industrystandard techniques while using commercially-available, commonlypracticed semiconductor device fabrication materials and techniques.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a method for repatterning circuits andthe like on semiconductor devices. The present invention relates to amethod for forming under bump metallization pads on semiconductordevices using simplified masking steps.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The advantages of the invention will be more readily understood from thefollowing description of the invention when taken in conjunction withthe accompanying drawings wherein:

FIGS. 1a-1 h are cross-sectional views of a prior art process of formingflip-chip solder bump connections; and

FIGS. 2a-2 h illustrate a method for repatterning the active surface ofa flip-chip.

DETAILED DESCRIPTION OF THE INVENTION

Referring to drawing FIGS. 2a-2 h, the method of the present inventionfor repatterning the circuits on a flip-chip is illustrated.Specifically, referring to drawing FIG. 2a, a semiconductor substrate orwafer 1004 includes a bond pad 1002 connected to a circuit 100. As shownin FIG. 2b, a first layer of passivation film 1006 is applied over aface surface or active surface 1010 of the semiconductor wafer 1004. Thepassivation layer 1006 is preferably a suitable polyamide layer. Thepolyamide passivation layer 1006 is typically formed by spin coating amixture of diamine and dianhydride monomers in a solvent, usuallyN-methyl-pyrrolidine 2 (NMP). Depending upon the predeterminedformulation of the polyamide, the thickness of the polyamide coating isdirectly related to the speed of rotation of the wafer. The monomerscombine at low temperature to form polyamic acid, which is soluble inNMP. The passivation film is subsequently dried at approximately 100° C.to initially remove most of the solvent and further dried at 250-400° C.to ensure complete solvent removal and the conversion to polyamide. Ifthe pyromellitic dianhydride-oxydianiline (PMDA-ODA) family ofpolyamides is used, such polyamides are isotropic in behavior, whilelong polymer chain biphenyldiaminine-phenyldiamine (BPDA-PDA) polyamidestend to be anisotropic in mechanical and electrical properties. Eithertype of polyamide can be used for the passivation layer. In this mannerthe polyamide is capable of absorbing the thin film stresses impartedfrom the deposition of the interconnection by the solder.

Still referring to drawing FIG. 2b, a photoresist 1005 is applied,masked and exposed (broken lines). The passivation film 1006 is thenetched using well known etching techniques to form a bond pad via 1008through the passivation film 1006 to the bond pad 1002, as shown.

Referring to drawing FIG. 2c, a conductive layer 1012, preferably asolder wettable metal, is applied over a face surface 1014 of thepassivation film 1006. The conductive layer is preferably a metal, suchas copper, nickel, palladium, platinum, gold, or alloys thereof, that iscapable of being easily wetted by solder and alloys thereof.

Referring to drawing FIG. 2d, the conductive layer 1012, shown in FIG.2c, is photoresist-coated, masked, exposed, and etched using well knowntechniques to form at least one conductive repattern trace 1016extending to a substitute or alternative bond pad location, as shown inFIG. 2d.

Referring to drawing FIG. 2e, a second passivation film 1018, such as aspin-on polyamide layer described hereinbefore, is applied over therepattern trace 1016, as shown.

Referring to drawing FIG. 2f, a suitable etch resistant layer 1020(photoresist) is applied over an upper surface 1022 of the secondpassivation film 1018, masked, and etched to form a resist via 1024 atthe alternative, repatterned bond pad location, as shown.

Referring to drawing FIG. 2g, a faceted or sloped-wall via 1026 is shownas etched according to the following preferred processes. A sputteretching process for forming sloped via 1026 begins with providing asemiconductor wafer assembly comprising a semiconductor wafer with aplurality of semiconductor elements (dice) including integratedcircuitry formed on the face (active) surface and with the plurality ofconductive traces and bond pads also formed on the semiconductor waferface surface positioned to contact respective semiconductor elementcircuitry. A passivation film is disposed over the semiconductor waferface surface, as well as the conductive traces and pads. A first layerof etch resist film, such as a photoresist, is applied to the facesurface of the passivation film, then masked, exposed, and stripped toform desired openings in the first etch resist film. After a shortperiod of time being subjected to sputter etching, sloped edges begin toform on the etch resist film as the wafer is sputtered and both resistfilm and passivation film are etched. The sputtering process continuesand sloped edges or walls begin to form in the passivation film afterthe resist is penetrated.

Alternately, a wet etching process for forming vias may be used. Theprocess begins with providing a semiconductor wafer assembly comprisinga semiconductor wafer with a plurality of semiconductor elements orcircuitry formed on the face surface and with the plurality ofconductive traces and bond pads also formed on the semiconductor waferface surface positioned to contact respective semiconductor elementcircuitry. A passivation film is disposed over the semiconductor waferface surface, as well as the conductive traces and pads. A first layerof etch resist film (photoresist or other film, depending upon theintended etchant and temperature) is applied to the face surface of thepassivation film. The first etch resist film is then masked, exposed,and stripped to form desired openings in the first etch resist film.

An appropriate acid, such as a 1:2 ratio mix of ammonium fluoride andacetic acid, or a 100:1 ratio mix of H₂O and HF acid for etching an SiOfilm, or hot (150-180° C.) phosphoric acid in the case of an Si₃N₄ film,is then applied to the surface of the wafer. Other suitable etchants, asknown in the art, may be employed in the case of polymer-based films,such as polyamides. After a short period of time of etching, a concaverecess begins to form on the passivation film. The process continuesuntil the etching forms the sloped via having somewhat arcuate or curvedsloped edges and which exposes the face surface of the conductiveelectrode. Resist is then stripped. An etch performed as described aboveforms a wall angle of the via with respect to the horizontal which isdesirable for solder ball formation by increasing surface area exposedto shear forces. Thus, as shown, a UBM structure is formed.

Referring to drawing FIG. 2h, a solder ball 1032 is formed in the via1026 in contact with the conductive repattern trace 1016.

It is, of course, understood that although the above description isgenerally directed to fabrication on a wafer scale, the method isequally applicable to single chips or portions of wafers.

It will also be understood that a solid preform comprising a “blank” ofsubstrate material (such as Si) may be employed over the exposed traceends of the wafer to define vias anisotropically wet-etched and platedwith metal to define the UBM. For purposes of this invention, a preformSi blank may also be considered as a passivation layer. Techniques forsuch via and UBM formation are disclosed in co-pending U.S. patentapplication Ser. No. 08/612,159, filed Mar. 7, 1996 and assigned to theassignee of the present invention, the disclosure of which isincorporated herein by this reference. The anisotropic wet etch of thesilicon blank may be effected by a KOH:H₂O mixture, resulting in apreferred 54° via wall angle to the horizontal for formation of a solderball therein.

Having thus described in detail the preferred embodiment of the presentinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description, as many apparent variations thereof are possiblewithout departing from the spirit or scope thereof.

What is claimed is:
 1. A method of forming portions of circuitsconnected to portions of integrated circuitry of a flip-chipsemiconductor substrate, said method comprising: forming a semiconductorsubstrate having integrated circuitry, having at least one surface andhaving at least one circuit on a portion of said at least one surface ofsaid semiconductor substrate connected to a portion of said integratedcircuitry and terminating in a bond pad, said at least one circuithaving a portion thereof covered by at least one first passivation layerwhile said bond pad remains substantially free of said at least onefirst passivation layer; forming a trace of solder wettable materialfrom said bond pad of said at least one circuit to another location onsaid at least one surface of said semiconductor substrate, said trace ofsaid solder wettable material contacting at least a portion of said bondpad of said at least one circuit and extending over a portion of said atleast one first passivation layer, said trace of said solder wettablematerial having a first surface and a second surface, a portion of saidsecond surface contacting said portion of said bond pad; forming atleast one second passivation layer over said portion of said at leastone surface of said semiconductor substrate and said trace of saidsolder wettable material; and etching a sloped-wall via through said atleast one second passivation layer extending to a portion of said firstsurface of said trace of solder wettable material at said anotherlocation on said at least one surface of said semiconductor substrate.2. The method of claim 1, wherein said etching is selected from a groupcomprising: sputter etching and wet etching.
 3. The method of claim 2,wherein said etching comprises sputter etching after application of aresist layer over said at least one second passivation layer, saidresist layer having an aperture therein aligned with said anotherlocation on said at least one surface of said semiconductor substrate.4. The method of claim 1, further comprising: depositing a solder massover said sloped-wall via.
 5. The method of claim 4, further comprising:liquefying said solder mass and cooling said solder mass to define asolder ball or bump.
 6. The method of claim 1, wherein said at least onecircuit is selected from a group consisting of bond pads and conductivetraces.
 7. A method of forming a metallization on a portion of a surfaceof a semiconductor substrate, said method comprising: forming asemiconductor substrate having integrated circuitry and having at leastone surface, said semiconductor substrate including at least one solderwettable trace on at least a portion of said at least one surfaceconnected to at least a portion of said integrated circuitry, saidsemiconductor substrate having at least one passivation layer over atleast a portion of said at least one solder wettable trace on said atleast a portion of said at least one surface; and forming a sloped-wallvia in a portion of said at least one passivation layer to expose aportion of said at least one solder wettable trace.
 8. The method ofclaim 7, wherein said forming said sloped-wall via comprises etching. 9.The method of claim 8, wherein said etching is selected from a groupconsisting of sputter etching and wet etching.
 10. The method of claim8, wherein said etching comprises sputter etching after application of aresist layer over said at least one passivation layer, said resist layerhaving an aperture therein aligned with said at least a portion of saidat least one solder wettable trace on said at least a portion of said atleast one surface of said semiconductor substrate.
 11. The method ofclaim 8, wherein said etching comprises wet etching effected afterapplication of a resist layer over said at least one passivation layer,said resist layer having an aperture therein aligned with said at leasta portion of said at least one solder wettable trace on said at least aportion of said at least one surface of said semiconductor substrate.12. A manufacturing method for an integrated circuit comprising: forminga substrate including integrated circuitry and at least one portion of atrace connected to said integrated circuitry, said at least one portionof said trace having one end thereof terminating in a bond pad; formingat least one first passivation layer over a portion of said at least oneportion of said trace while said bond pad remains substantially free ofsaid at least one passivation layer; forming another trace in contactwith at least a portion of said bond pad of said at least one portion ofsaid trace, a portion of said another trace extending over a portion ofsaid at least one first passivation layer, said another trace having anupper surface; forming at least one second passivation layer over saidportion of said another trace; forming a sloped-wall via through said atleast one second passivation layer extending to a portion of said uppersurface of said another trace; and forming a solder mass having aportion extending into said sloped-wall via contacting said portion ofsaid upper surface of said another trace.
 13. The manufacturing methodof claim 12, wherein said another trace comprises a solder wettablematerial.
 14. The manufacturing method of claim 13, wherein said solderwettable material comprises copper, nickel, palladium, platinum, gold,or an alloy thereof.
 15. A manufacturing method for an integratedcircuit comprising: forming a substrate including integrated circuitryhaving a portion thereof located on a portion of a surface of saidsubstrate, another portion of said integrated circuitry terminating inat least one bond pad, at least one trace located on said portion ofsaid surface of said substrate connected to said at least one bond padof said integrated circuitry and having at least one passivation layerover at least said portion of said surface of the substrate; forming asloped-wall via through a portion of said at least one passivation layerover said at least said portion of said surface of said substrate toexpose one of at least a portion of said at least one trace and aportion of said at least one bond pad; and forming a solder mass havinga portion extending into said sloped-wall via contacting one of saidportion of said at least one trace and said portion of said at least onebond pad.
 16. The manufacturing method of claim 15, wherein said atleast one trace comprises a solder wettable material.
 17. Themanufacturing method of claim 16, wherein said solder wettable materialcomprises copper, nickel, palladium, platinum, gold, or an alloythereof.
 18. The manufacturing method of claim 15, wherein said one ofsaid at least a portion of said at least one trace and said portion ofsaid at least one bond pad comprises copper, nickel, palladium,platinum, gold or an alloy thereof.
 19. The manufacturing method ofclaim 18, wherein said one of said at least a portion of said at leastone trace and said portion of said at least one bond pad comprisescopper, nickel, palladium, platinum, gold, or an alloy thereof.